As known in the art, TSVs which are also referred to as through-wafer vias (TWVs), are vertical electrical connections that pass from the frontside surface of a wafer or IC die (e.g., contact level or one of the metal levels) completely through to the backside surface. As a result, electrical paths through the device can be significantly shortened relative to conventional wire bonding technology, leading to significantly faster device operation and smaller footprints because the interconnect is within the footprint of the IC die and thus does not require any additional area.
Regarding fabrication of TSVs, in a conventional via-first process, vias are formed through the top semiconductor comprising surface of the wafer in the front end of the line (FEOL) portion of the process using chemical etching, laser drilling, or one of several energetic methods, such as Reactive Ion Etching (RIE). The vast array of vias must be accurately located and have an acceptable cross-sectional profile. Once the through-vias are formed, they are framed with a dielectric liner (e.g., thermally grown silicon oxide) and are then filled with an electrically conductive filler material. Copper plating, preceded by barrier layer and seed layer deposition, represents a conventional TSV filling method, although through-vias can also be filled using other methods and with other electrically conductive filler materials (e.g., W, or highly doped polysilicon).
As known in the art, low resistance electrical ground connections in IC's, particularly for certain RF devices, are required for proper device function. In the case of TSV technology, one or more of the TSVs can be used for ground connections to the front side of the IC through coupling to a grounded electrical conductor that is beneath the bottom surface of the IC.
In one known arrangement, an anisotropic conducting film (ACF) is used between the TSV tip(s) and a package substrate (e.g., die pad) to reduce the resistance (and inductance) between the TSV tip(s) and the package substrate as compared to a bond wire connection. The TSV tips penetrate into the ACF. The ACF includes a plurality of electrically conductive particles electrically isolated from one another by a dielectric base material, such as an epoxy. Although the ACF arrangement reduces the electrical resistance between the TSV tips and the package substrate somewhat, the reduction is limited because the ACF particles are generally 3-5 μm in size (and are thus significantly smaller than the typical distance between the TSV tip(s) and a package substrate) and the particle loading is such that the statistical probability of trapping enough (if any) particles beneath the TSV tip diameter to make a low resistance electrical joint is low. Accordingly, the minimum nominal resistance between the TSV tips and the package substrate (e.g., die pad) provided by the ACF arrangement is still generally too high for proper performance of certain analog ICs, in particular for certain RF ICs, such as power amplifiers.